The present invention pertains to the field of desynchronizers. More particularly, the present invention pertains to an apparatus for implementing a desynchronizer in a way that reduces output jitter, especially output jitter caused by bit and byte justifications in the input to a desynchronizer.
Jitter is a term used to refer to fluctuations above a certain frequency in the bit rate of a signal. It is known that it is necessary to control jitter at the output of a desynchronizer connecting a Synchronous Digital Hierarchy (SDH) Network, or, equivalently, Synchronous Optical Network (SONET), to a Plesiochronous Digital Hierarchy (PDH) network. A desynchronizer is used to extract from an SDH signal a particular PDH signal. The output of the desynchronizer providing the PDH signal can have unacceptable jitter either because the SDH source used bit justification in encoding the PDH signal within the SDH signal, or because byte justification was used by some upstream SDH source to account for clock irregularities or frequency offsets between clocks.
In essence, the function of a desynchronizer is to extract from a composite signal a particular component, or tributary, that contains, in a frame structure having overhead and a payload, PDH data as its payload. Then the desynchronizer reads only the PDH data into a buffer from which it is able to output the PDH data at a particular output rate. The output rate is of course a fraction of the input data rate, i.e. the rate at which the desynchronizer reads the composite signal, but is necessarily great enough that the buffer does not overflow. Since the data to be output arrives irregularly however, even without any clock irregularity or bit or byte justification upstream of the desynchronizer, the desynchronizer must use a buffer in order to output data bits at a smooth, regular rate. The average rate at which data arrives at the buffer must equal the average rate at which data is read out of the buffer. With upstream bit and byte justifications, the desynchronizer must account for added irregularity in the rate at which the data arrives at the buffer.
For example, one component of an SDH signal, the tributary unit-12 (TU-12) component, which corresponds to an E1 PDH signal, may be conveyed by the TU-12 component of an SDH signal, extracted by a desynchronizer, and provided by the desynchronizer to a PDH network. An E1 signal is the European primary rate PDH signal, and it has a nominal bit rate of 2.048 Mbits/sec. Both the SDH and PDH signals are organized as frames consisting of an overhead part and a payload part. The source of the SDH signal may encode the E1 signal within the payload of a frame of the TU-12 component and, from time to time, use bit justification (positive or negative) to adjust to the pace at which it receives E1 data.
Bit justification can be either positive or negative. In negative bit justification, the source that provides the TU-12 frames conveying the E1 data uses, from time to time, some of the overhead, in addition to the payload, to convey E1 data, thereby increasing the rate of output, which it does in order to keep pace with the rate at which it receives E1 data. Alternatively, the source may, from time to time, not use the full amount of the TU-12 payload to convey E1 data, thereby slowing the pace at which it outputs the E1 signal, again to keep pace with the rate at which it receives E1 data. This procedure is termed positive bit justification.
Bit justification does not appear as jitter at the output of a source providing a TU-12 signal, because the bits are stuffed in TU-12 frames that always have the same number of bytes. However, in extracting an E1 signal from TU-12 frames, a desynchronizer encounters clumps of different numbers of bits of E1 data, the difference from clump to clump resulting from the bit and byte justifications. In providing the E1 signal to the PDH network, a desynchronizer produces output jitter as it leaks the justification bits onto the PDH network.
In the case of providing an E1 signal from a TU-12 component of an SDH signal, the term jitter is used to refer to all fluctuations above some frequency in the clock used to control output to the PDH network. (Lower frequency fluctuations are termed "wander".) Jitter performance is characterized in ITU-T Recommendation G.783, "Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks," 1994, which is hereby incorporated by reference.
Part of the SDH signal, referred to as the tributary unit-12 (TU-12) component, contains the data of the PDH signal as well as overhead bits. In the prior art, as in the present invention, all of the SDH bits except for the PDH data are dropped out of a desynchronizer. To do this, the desynchronizer typically has a buffer and writes only the PDH data into the buffer using first a clock gapped to correspond only to the TU-12 component of the full incoming SDH synchronous transport module-N (STM-N) signal of the desynchronizer node. Then, using a circuit to detect overhead and justification bits of an SDH signal and the TU-12 clock signal, the desynchronizer creates a further gapped clock corresponding only to the E1 PDH data conveyed by the TU-12 component of the SDH signal. The desynchronizer uses this twice-gapped clock to write to its buffers only the PDH data in the input signal.
To clock the data out of the buffer at an approximately constant rate, the desynchronizer must smooth the twice-gapped write clock to produce a regular (non-gapped) read clock for outputting the PDH data. To provide this smoothed output at a rate that prevents overflow of the buffer, a prior art desynchronizer may use a phase-locked loop (PLL) that includes a stable clock signal from which it derives the rate at which data is output.
The prior art often uses a phase locked loop, with at least one analog component, comprising a phase detector, filter, and voltage-controlled oscillator. In a typical analog/digital PLL, the phase detector and filter are digital, and the voltage-controlled oscillator (VCO) is analog. The performance of any of these PLLs varies with age, temperature, and voltage fluctuations. All-digital PLLs obviously replace the analog components with their digital counterparts. For example, an all-digital PLL uses a digitally-controlled oscillator instead of a VCO, and its performance is far less sensitive to age, temperature, and voltage fluctuations. Other benefits of an all-digital phase locked loop include a narrower bandwidth, a higher operating frequency, and higher-order loops. W. T. Greer, Jr., "Digital Phase-Locked Loops Move Into Analog Territory," Electronic Design, Mar. 31, 1982, pp. 95-100.
Thus, the prior art provides for either good jitter control and undesired complexity, or else inadequate jitter control. What is needed is a desynchronizer that has very good jitter performance and yet has a low-level of complexity so that it is feasible to implement.